1. Field of the Invention
The present invention relates to an image processing scheme, and more particularly, to an image processing method capable of reducing total circuit costs and computation complexity, and an apparatus thereof.
2. Description of the Prior Art
When proceeding with a block matching operation, a conventional image processing scheme usually takes account of multiple image blocks within a predetermined two-dimensional range in a previous image and then, among the image blocks, looks for the image block that is the most similar to a certain image block in a current image, to determine a motion vector. In practice, however, during the block matching operation, it is necessary to perform calculations for a large number of pixels, and the related computation procedure is very complicated. More line buffers are necessary since the line buffers used for storing pixel data need to buffer a large amount of pixel data. In this situation, ten or twenty line buffers are required in general. Thus, the total circuit costs for the conventional image processing scheme increase due to having more line buffers, and a longer computation period is necessary for completing the block matching operation.